View ISL70002SEHEVAL1Z_4644785.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 rad hard and see hard 12a synchronous buck regulator with multi-phase current sharing isl70002seh the isl70002seh is a radiatio n hardened and see hardened high efficiency monolithic synchronous buck regulator with integrated mosfets. this single chip power solution operates over an input voltage range of 3v to 5.5v and provides a tightly regulated output voltage that is externally adjustable from 0.8v to ~85% of the input voltage. output load current capacity is 12a for t j +150c. two isl70002seh devices configured to current share can provide 19a to tal output current, assuming 27% worst-case current share accuracy. the isl70002seh utilizes peak current-mode control with integrated error amp compensation and pin selectable slope compensation. switching frequency is also pin selectable to either 1mhz or 500khz. two isl70002seh devices can be synchronized 180 out-of-phase to reduce input rms ripple current. high integration makes the isl7 0002seh an ideal choice to power small form factor applications. two devices can be synchronized to provide a complete power solution for large scale digital ics, like field pr ogrammable gate arrays (fpgas), that require separate core and i/o voltages. applications ? fpga, cpld, dsp, cpu core and i/o voltages ? low-voltage, high-density distributed power systems features ?dla smd#5962-12202 ? 12a output current for a single device (at t j = +150 c) ? 19a output current for two paralleled devices ? 1mhz or 500khz switching frequency ? 3v to 5.5v supply voltage range ? 1% ref. voltage (line, load, temp. & rad.) ? pre-biased load compatible ? redundancy/junction isolation: exceptional set performance ? excellent transient response ? high efficiency > 90% ? two isl70002seh synchronization, inverted-phase ? comparator input for enable and power-good ?adjustable analog soft-start ? input undervoltage, output undervoltage and adjustable output overcurrent protection ? qml qualified per mil-prf-38535 ? full mil-temp range operation (-55 c to +125 c) ? radiation environment - high dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 krad(si) - eldrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 krad(si)* *level guaranteed by charac terization; ?eh? version is production tested to 50 krad(si). ? see hardness - sel and seb let th . . . . . . . . . . . . . . . . . . 86.4mev/mg/cm 2 -sefi let th . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43mev/mg/cm 2 -set let th . . . . . . . . . . . . . . . . . . . . . . . . . . 86.4mev/mg/cm 2 70 75 80 85 90 efficiency (%) load current (a) 0123456789 figure 1. efficiency 5v input to 2.5v output, t a = +25c 10 11 12 ch4 sync ch3 vout x 10 ch2 slave lx + 15v ch1 master lx + 20v -6 -4 -2 0 2 4 6 8 10 12 14 time (s) amplitude (v) 25 20 15 10 5 0 figure 2. 2-phase set performance at 86.4mev/mg/cm 2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. april 5, 2012 fn8264.1
isl70002seh 2 fn8264.1 april 5, 2012 functional block diagram power-on reset (por) pwm reference 0.6v soft start compensation ea gm slope compensation gate drive current sense lxx pvinx fb uv pgood power-good pgndx avdd ss m/s sync porsel ref tdi tdo bit tpgm trim agnd dvdd dgnd en trim sc0 sc1 overcurrent adjust ocssa ocssb oca ocb fsel current share pwm control logic ishrefa ishrefb ishrefc isha ishb ishc ishen ishsl ishcom gnd pgndx pgndx ordering information ordering number part number (notes 1, 2) temp. range (c) package (rohs compliant) pkg. dwg. # 5962r1220201vxc isl70002sehvf -55 to +125 64 ld cqfp r64.a 5962r1220201v9a isl70002sehvx -55 to +125 die isl70002sehf/proto isl70002sehf/proto -55 to +125 64 ld cqfp r64.a isl70002sehx/sample isl70002sehx/sample -55 to +125 die ISL70002SEHEVAL1Z evaluation board note: 1. these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant and c ompatible with both snpb and pb-free soldering operations. 2. for moisture sensitivity level (msl), please see device information page for isl70002seh . for more information on msl please see techbrief tb363 .
isl70002seh 3 fn8264.1 april 5, 2012 pin configuration isl70002seh (64 ld cqfp) top view ishc ishrefb ishb ishrefa isha fb 1 2 3 4 5 6 7 8 9 10 11 17 18 19 20 21 22 ishrefc avdd agnd dgnd dvdd 43 42 41 40 39 38 27 26 25 24 23 pvin6 lx6 pgnd6 pgnd5 lx5 pvin5 59 58 57 56 55 54 48 47 46 45 44 64 63 62 61 60 en pvin1 lx1 pgnd1 pgnd2 lx2 lx3 pgnd3 pgnd4 lx4 pvin4 ref oca ocssa ocb ocssb 28 32 31 30 29 53 52 51 50 49 pvin2 sc1 sc0 nc pvin3 ss 12 13 14 15 16 pgood ishcom ishsl ishen 37 36 35 34 33 lx8 pgnd8 pgnd7 lx7 pvin7 lx9 pgnd9 pgnd10 lx10 pvin10 sync pvin8 nc fsel m/s pvin9 gnd tpgm tdi tdo porsel pin descriptions pin number pin name description 1 fb this pin is the voltage feedback input to the internal error amplifier. connect a resi stor from fb to vout and from fb to agnd to adjust the output voltage in accordance with equation 1: where: v out = output voltage v ref = reference voltage (0.6v typical) r t = top divider resistor (must be 1k ) r b = bottom divider resistor the top divider resistor must be 1k to mitigate see. connect a 4.7nf cera mic capacitor across rt to mitigate see and to improve stability margins. if using current share, tie fb of the master to fb of the slave. 2, 4, 6 isha/b/c if configured as a current share master (ishsl = dgnd, ishen = dvdd), the is ha/b/c pins are outputs that provides a current equal to 25 ti mes the redundant a/b/c error amp output currents plus ishrefa/b/c (nominally 100a each). if configured as a current share slave (ishsl = dvdd, ishen = dvdd), the isha/b/c pins are inputs that become the slave?s redundant a/b/ c error amp output current. if using current share, tie isha/b/c of the master to isha/b/c of the slave. if not using current share, tie isha/b/c to dvdd. isha/b/c are tri-stated prior to a valid por and when ishen = dgnd. v out v ref 1r t r b ? () + [] ? = (eq. 1)
isl70002seh 4 fn8264.1 april 5, 2012 3, 5, 7 ishrefa/b/c if configured as a current share master (ishsl = dgnd, ishen = dvdd), the ishrefa/b/c pins provide a reference output current equal to 100ua each. if co nfigured as a current share slave (ishsl = dvdd, ishen = dvdd), the ishrefa/b/c pins accept a reference input current. for a current share slave, this input current is used together with the isha/b/c current to determine the master?s redundant a/b/c error amp output current. if using current share, tie ishrefa/b/c of the ma ster to ishrefa/b/c of the slave. if not using current share, tie ishrefa/b/c to dvdd. the purpose of the reference current is to reduce the impact of external noise coupling onto isha/b/c. ishr efa/b/c are tri-stated prior to a valid por and when ishen = dgnd. 8 avdd this pin is the bias supply input to the internal analog control circuitry. lo cally filter this pin to agnd using a 1 resistor and a 1f ceramic capacitor. locate both filter components as close as possible to the ic. avdd should be the same voltage as dvdd and pvinx (200mv). 9 agnd this pin is the analog ground associ ated with the internal analog control circuitry. connect this pin directly to the pcb ground plane. 10 dgnd this pin is the digital ground associ ated with the internal digital control circ uitry. connect this pin directly to the pcb ground plane. 11 dvdd this pin is the bias supply input to the internal digital control circuitry. locally filter this pin to dgnd using a 1 resistor and a 1f ceramic capacitor. locate both filter components as close as possible to the ic. dvdd should be the same voltage as avdd and pvinx (200mv). 12 ss this pin is the soft-start input. co nnect a ceramic capacitor from this pin to dgnd to set the soft-start output ramp time in accordance with equation 2: where: t ss = soft-start output ramp time c ss = soft-start capacitor v ref = reference voltage (0.6v typical) i ss = soft-start charging current (23a typical) soft-start time is adjustable from approximately 2ms to 200ms. the range of the soft-start capacitor should be 82nf to 8.2f, inclusive. if using current share, c ss of the slave should be at least twice the c ss of the master. 13 pgood this pin is the power-good output. this pin is an open drain logic output that is pulled to dgnd when the output voltage is outside a 11% typical regulation window. this pin can be pulled up to any voltage from 0v to 5.5v, independent of the supply voltage. a nominal 1k to 10k pull-up resistor is recommended. bypass this pin to dgnd with a 10nf ceramic capacitor to mitigate see. if using current share, tie pgood of the master to pgood of the slave. 14 ishcom ishcom is a bidirectional communication line between a current share master and a current share slave. if using current share, tie ishcom of the master to ishcom of the slave. the master enables the slave by resistively (~ 8.5k ) pulling ishcom high. the slave indicates an ov er-current fault condition to the master by pulling ishcom low. to mitigate set, connect a 47pf ce ramic capacitor from ishcom to the pcb ground plane. if not using current share this pin should be floated or connected to the pcb ground plane. ishcom is tri-stated if ishen is low. 15 ishsl this pin is a logic input that is used to configure the ic as a current share master or slave. tie this pin to dvdd to configure the ic as a current share slave. tie this pin to the pcb ground plane to configure the ic as a current share master, or if the current share feature is not being used. 16 ishen this pin is an input that enables/disables the current share feature. to enable the cu rrent share feature, tie this pin to dvdd. to disable the current share feature, tie this pin to the pcb ground plane. 17 porsel this pin is the input for selecting the rising and falling por (power-on-reset) thresholds. for a nominal 5v supply, connect this pin to dvdd. for a nominal 3.3v supply, connect this pin to dgnd. for nominal supply voltages between 5v and 3.3v, connect this pin to dgnd. 18 tdo this pin is the test data output of the internal bit circuitry. connect this pin to the pcb ground plane. 19 tdi this pin is the test data input of the internal bi t circuitry. connect this pin to the pcb ground plane. 20 tpgm this pin is a trim input and is used to adjust various internal circuitry. connect this pin to the pcb ground plane. 21 gnd this pin is connected to an internal metal die trace th at serves as a sensitive node noise shield. connect this pin to the pcb ground plane. pin descriptions (continued) pin number pin name description t ss c ss v ref ? i ss ? = (eq. 2)
isl70002seh 5 fn8264.1 april 5, 2012 22 sync when sync is configured as an output (clock mast er mode, m/s = dvdd), this pin drives the sync input of another isl70002seh with a square ware that is invert ed (~180 out-of-phase) from the master clockdriving the master pwm circuits. when configured as an input (c lock slave mode, m/s = dgnd), this pin uses the sync output from another isl70002seh or an external clock to drive the clock slave pwm circuitry. if synchronizing to an external clock, the clock must be see hardened and the frequency must be within the range of 400khz to 1.2mhz. 23, 28, 32, 37, 38, 43, 44, 49, 53, 58 pvinx these pins are the power supply inputs to the corr esponding internal power blocks. these pins must be connected to a common power supply rail, which must fall in the range of 3v to 5.5v. bypass these pins directly to pgndx with ceramic capacitors located as close as po ssible to the ic. pvinx should be the same voltage as dvdd and avdd (200mv). 24, 27, 33, 36, 39, 42, 45, 48, 54, 57 lxx these pins are the outputs of the corresponding internal power blocks and should be connected to the output filter inductor. internally, these pins are conne cted to the synchronous mosfet power switches. 25, 26, 34, 35, 40, 41, 46, 47, 55, 56 pgndx these pins are the power grounds associated with th e corresponding internal power blocks. these pins also provide the ground path for the metal package lid. connec t these pins directly to the pcb ground plane. these pins should also connect to the nega tive terminals of the input and output capacitors. locate the input and output capacitors as close as possible to the ic. 29 m/s this pin is the clock master/slave input for select ing the direction of the bi-directional sync pin. for sync = output (master mode), connect this pin to dvdd. fo r sync = input (slave mode), connect this pin to the pcb ground plane. 30 fsel this pin is the oscillator frequency select input. ti e this pin to dvdd to select a 1mhz nominal oscillator frequency. tie this pin to the pcb ground plane to select a 500khz nominal oscillator frequency. 31, 50 nc these are no connect pins that are not connected to anything internally. they should be connected to the pcb ground plane. 51, 52 sc0/1 these pins are inputs that co mprise a 2-bit code to select the slope compensation (sc) current ramp referred to the output as shown below. sc1 = dvdd, sc0 = dvdd: sc = 6.6a/s for fsel = dgnd sc1 = dvdd, sc0 = dgnd: sc = 3.3a/s for fsel = dgnd sc1 = dgnd, sc0 = dvdd: sc = 1.6a/s for fsel = dgnd sc1 = dgnd, sc0 = dgnd: sc = 0.8a/s for fsel = dgnd sc1 = dvdd, sc0 = dvdd: sc= 13.4a/s for fsel = dvdd sc1 = dvdd, sc0 = dgnd: sc = 6.7a/s for fsel = dvdd sc1 = dgnd, sc0 = dvdd: sc = 3.4a/s for fsel = dvdd sc1 = dgnd, sc0 = dgnd: sc = 1.7a/s for fsel = dvdd if using current share, sc0 and sc1 of th e slave must match the master sc0 and sc1. 59 en this pin is the enable input to the ic. this is a co mparator type input with a rising threshold of 0.6v and programmable hysteresis. driving this pin above 0.6v enab les the ic. bypass this pin to the pcb ground plane with a 10nf ceramic capacitor to mitigate see. 60, 62 ocssb/a this pin is a switch to agnd that is active during the soft-start period. it is used to set the redundant a/b peak overcurrent limit threshold during so ft-start. connect a resistor from oc ssx to ocx in accordance with the following equation: rocssx 600mv / [(iocssx - iocx) /100,000] where iocx is the desired peak overcurrent limit duri ng normal operation and iocssx is the desired peak current limit threshold during soft-start. 61, 63 ocb/a this pin is a source follower output that is used to set the redundant a/b peak overcurrent limit threshold during normal operation. connect a resistor from this pin to the pcb ground plane in accordance with the following equation: rocx = 600mv / (iocx /100,000), where iocx is the desired peak current limit threshold during normal operation. 64 ref this pin is the internal reference voltage output. bypa ss this pin to the pcb ground plane with a 220nf ceramic capacitor located as close as possible to the ic. the by pass capacitor is needed to mitigate see. no current (sourcing or sinking) is available from this pin. if using current share, tie ref of the master to ref of the slave through a 10 resistor. pin descriptions (continued) pin number pin name description
isl70002seh 6 fn8264.1 april 5, 2012 typical application schematic figure 3. single unit operation fb ishb isha ishc ishrefa ishrefc ishrefb avdd agnd dgnd dvdd ss 2 4 6 1 3 5 7 8 9 10 12 11 pgood ishcom ishsl ishen porsel tdo tdi tpgm gnd sync pvin1 pvin2 pvin3 pvin4 pvin5 pvin6 pvin7 pvin8 pvin9 pvin10 13 15 14 16 18 17 19 20 21 22 23 28 32 37 38 43 44 49 53 58 lx2 lx3 lx4 lx5 lx6 lx7 lx8 lx9 lx10 27 33 36 39 42 45 48 54 57 lx1 24 pgnd2 pgnd3 pgnd4 pgnd5 pgnd6 pgnd7 pgnd8 pgnd9 pgnd10 26 34 35 40 41 46 47 55 56 pgnd1 25 m/s 29 fsel 30 nc nc 31 50 sc0 sc1 52 51 en 59 ocssa ocssb 60 62 oca ocb 61 63 ref 64 isl70002seh 500nh 1f + 6x150f 1.8 1nf 19.6k 19.6k 0.1f 0.22f 1 1 4.02k 4.02k 6.8nf 6.8nf 1k 1.5k vout avdd 1k 10nf 1f 1f vin + 6x150f 5 x 1f avdd 47pf
isl70002seh 7 fn8264.1 april 5, 2012 figure 4. two phase operat ion with current sharing typical application schematic (continued) fb ishb isha ishc ishrefa ishrefc ishrefb avdd agnd dgnd dvdd ss 2 4 6 1 3 5 7 8 9 10 12 11 pgood ishcom ishsl ishen porsel tdo tdi tpgm gnd sync pvin1 pvin2 pvin3 pvin4 pvin5 pvin6 pvin7 pvin8 pvin9 pvin10 13 15 14 16 18 17 19 20 21 22 23 28 32 37 38 43 44 49 53 58 lx2 lx3 lx4 lx5 lx6 lx7 lx8 lx9 lx10 27 33 36 39 42 45 48 54 57 lx1 24 pgnd2 pgnd3 pgnd4 pgnd5 pgnd6 pgnd7 pgnd8 pgnd9 pgnd10 26 34 35 40 41 46 47 55 56 pgnd1 25 m/s 29 fsel 30 nc nc 31 50 sc0 sc1 52 51 en 59 ocssa ocssb 60 62 oca ocb 61 63 ref 64 isl70002seh 500nh 1f + 3x150f 1.8 1nf 19.6k 19.6k 0.1f 0.22f 1 1 4.02k 4.02k 6.8nf 6.8nf 1k 1.5k vout 1k 10nf 1f 1f vin + 6x150f 5 x 1f fb avdd agnd dgnd dvdd ss 1 8 9 10 12 11 pgood porsel tdo tdi tpgm gnd sync pvin1 pvin2 pvin3 pvin4 pvin5 pvin6 pvin7 pvin8 pvin9 pvin10 13 18 17 19 20 21 22 23 28 32 37 38 43 44 49 53 58 lx2 lx3 lx4 lx5 lx6 lx7 lx8 lx9 lx10 27 33 36 39 42 45 48 54 57 lx1 24 pgnd2 pgnd3 pgnd4 pgnd5 pgnd6 pgnd7 pgnd8 pgnd9 pgnd10 26 34 35 40 41 46 47 55 56 pgnd1 25 m/s 29 fsel 30 nc nc 31 50 sc0 sc1 52 51 en 59 ocssa ocssb 60 62 oca ocb 61 63 ref 64 isl70002seh 500nh 1f + 3x150f 1.8 1nf 19.6k 19.6k 0.22f 0.22f 1 1 4.02k 4.02k 6.8nf 6.8nf vout 1f 1f vin + 6x150f 5 x 1f ishb isha ishc ishrefa ishrefc ishrefb 2 4 6 3 5 7 ishcom ishsl ishen 15 14 16 10 dvdd2 dvdd2 dvdd1 dvdd1 47pf
isl70002seh 8 fn8264.1 april 5, 2012 fse v absolute maximum ratings (note 3) thermal information avdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . agnd - 0.3v to agnd + 6.2v dvdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dgnd - 0.3v to dgnd + 6.2v lxx, pvinx (note 8) . . . . . . . . . . . . . . . . . . . pgndx - 0.3v to pgndx + 6.2v avdd - agnd, dvdd - dgnd . . . . . . . . . . . . . . . . . . . pvinx - pgndx 0.3v signal pins (note 6) . . . . . . . . . . . . . . . . . . . . . .agnd - 0.3v to avdd + 0.3v digital control pins (note 7) . . . . . . . . . . . . . . dgnd - 0.3v to dvdd + 0.3v pgood . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dgnd - 0.3v to dgnd + 6.2v ss. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dgnd - 0.3v to dgnd + 2.5v thermal resistance ja (c/w) jc (c/w) cqfp package (notes 4, 5) . . . . . . . . . . . . . 34 1.5 operating junction temperature range . . . . . . . . . . . . . -55c to +150c storage temperature range . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions avdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . agnd + 3v to 5.5v dvdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dgnd + 3v to 5.5v pvinx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pgndx + 3v to 5.5v avdd - agnd, dvdd - dgnd . . . . . . . . . . . . . . . . . . . pvinx - pgndx 0.1v signal pins (note 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .agnd to avdd digital control pins (note 7) . . . . . . . . . . . . . . . . . . . . . . . . . . dgnd to dvdd ref, ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . internally set gnd, tdi, tdo, tpgm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dgnd i lxx (t j +150c). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0a to 1.2a ambient temperature range . . . . . . . . . . . . . . . . . . . . . . -55c to +125c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 3. absolute maximum ratings assume operation in a heavy ion environment. 4. ja is measured in free air with the component mounted on a high effective thermal conductivity test board. see tech brief tb379 for details. 5. for jc , the ?case temp? location is the center of the package underside. 6. en, fb, ishx, ishrefx, ocx, ocssx, porsel and ref pins. 7. fsel, gnd, ishcom, ishen, ishrsl, m/s, sync, sc0, sc1, tdi, tdo and tpgm pins. 8. the 6.2v absolute maximum rating must be met for a 20mhz band width limited observation at the device pins. in addition, for a 600mhz bandwidth limited observation, the peak transient voltag e on pvinx (measured to pgndx) must be less than 7.1v with a duration above 6.2 v of less than 10ns, and the peak transient voltage on lxx (measured to pgndx) must be less than 7.9v with a duration above 6.2 v of less than 10ns. electrical specifications unless otherwise noted, v in = avdd = dvdd = pvinx = en = fsel = m/s = sc0 = sc1= 3v to 5.5v; gnd = agnd = dgnd = pgndx = ishx = ishcom = ishen = ishrefx = ishsl = tdi = tdo = tpgm = 0v; fb = 0.65v; porsel = v in for 4.5v v in 5.5v and gnd for v in < 4.5v; lxx = sync = open circuit; ocx is connected to ocssx with a 10k resistor; ocx is connected to gnd with a 4.99k resistor shunted by a 6.8nf capa citor; pgood is pulled up to v in with a 1k resistor; ref is bypassed to gnd with a 220nf capacitor; ss is bypassed to gnd with a 100nf capacitor; t a = t j = -55c to +125c; post 100krad(si). (note 6). parameter test conditions min (note 10) typ max (note 10) units power supply operating supply current (current share disabled) v in = 5.5v 70 105 ma v in = 3.6v 43 65 ma standby supply current (current share disabled) v in = 5.5v, en = gnd, ishen = gnd 2.5 6 ma v in = 3.6v, en = gnd, ishen = gnd 2 4 ma operating supply current (current share enabled, current share master) v in = ishen = 5.5v, ishcom = open circuit 70 120 ma operating supply current (current share enabled, current share slave) v in = ishen = ishsl = 5.5v, ishcom pulled to v in with 1k , m/s = gnd, ishx = ishrefx = -100a, sync = external 1mhz clock 70 120 ma standby supply current (current share enabled, current share slave) v in = ishen = ishsl = 5.5v, en = m/s = gnd, sync = external 1mhz clock 3.0 7 ma v in = ishen = ishsl = 5.5v, m/s = gnd, sync = external 1mhz clock, ishcom = gnd 7.3 11 ma output voltage & current reference voltage 0.594 0.6 0.606 v
isl70002seh 9 fn8264.1 april 5, 2012 output voltage tolerance v out = 0.8v to 2.5v, i out = 0a to 12a (notes 11, 12) -2 2 % error amp input offset voltage v in = 5.5v, v ref = 600mv, test mode -1 3 mv feedback (fb) input leakage current v in = 5.5v, v fb = 600mv -1.5 1.5 a sustained output current v in = 3v, v out = 1.8v, oca = ocb = pvin (note 13) 16 22 a pwm control logic internal oscillator tolerance fsel = v in or gnd -15 15 % external oscillator range m/s = gnd 0.4 1.2 mhz minimum lxx on time v in = 5.5v, test mode 200 275 ns minimum lxx off time v in = 5.5v, test mode 0 50 ns minimum lxx on time v in = 3v, test mode 225 300 ns minimum lxx off time v in = 3v, test mode 0 50 ns porsel, master/slave (m/s), sc1, sc0, ishsl, ishen, fsel input voltage input high threshold v in -0.5 1.3 v input low threshold 1.2 0.5 v porsel, master/slave (m/s), sc1, sc0, ishsl, ishen, fsel input leakage current v in = 5.5v -1 1 a synchronization (sync) input voltage input high threshold, m/s = gnd 2.3 1.7 v input low threshold, m/s = gnd 1.5 1 v synchronization (sync) input leakage current v in = 5.5v, m/s = gnd, sync = v in or gnd -1 1 a synchronization (sync) output voltage v in - v oh @ i oh = -1ma 0.1 0.4 v v ol @ i ol = 1ma 0.1 0.4 v power blocks upper device r ds(on) v in = 3v, 4a load, all power blocks in parallel, test mode (note 9) 20 40 m lower device r ds(on) v in = 3v, 4a load, all power blocks in parallel, test mode (note 9) 15 30 m lxx output leakage v in = 5.5v, en = lxx = gnd, single lxx output -1 a v in = lxx = 5.5v, en = gnd, single lxx output 10 a deadtime (note 12) within a single power block or between power blocks 2.2 25 ns efficiency (note 12) v in = 3.3v, v out = 1.8v, i out = 6a, fsel = gnd 88 % v in = 5v, v out = 2.5v, i out = 6a 90 % power-on reset vin por rising threshold, porsel = v in 4.1 4.3 4.45 v hysteresis, porsel = v in 225 325 425 mv rising threshold, porsel = gnd 2.65 2.8 2.95 v hysteresis, porsel = gnd 70 140 240 mv enable (en) input voltage rising/falling threshold 0.56 0.6 0.64 v enable (en) input leakage current v in = 5.5v, en = v in or gnd -3 3 a electrical specifications unless otherwise noted, v in = avdd = dvdd = pvinx = en = fsel = m/s = sc0 = sc1= 3v to 5.5v; gnd = agnd = dgnd = pgndx = ishx = ishcom = ishen = ishrefx = ishsl = tdi = tdo = tpgm = 0v; fb = 0.65v; porsel = v in for 4.5v v in 5.5v and gnd for v in < 4.5v; lxx = sync = open circuit; ocx is connected to ocssx with a 10k resistor; ocx is connected to gnd with a 4.99k resistor shunted by a 6.8nf capa citor; pgood is pulled up to v in with a 1k resistor; ref is bypassed to gnd with a 220nf capacitor; ss is bypassed to gnd with a 100nf capacitor; t a = t j = -55c to +125c; post 100krad(si). (note 6). (continued) parameter test conditions min (note 10) typ max (note 10) units
isl70002seh 10 fn8264.1 april 5, 2012 enable (en) sink current en = 0.3v 6.4 11 16.6 a soft-start soft-start source current ss = gnd 20 23 27 a soft-start discharge on-resistance 2.2 4.7 soft-start discharge time 256 clock cycles power-good signal rising threshold v fb as a % of v ref , test mode 107 111 115 % rising hysteresis v fb as a % of v ref , test mode 2 3.5 5 % falling threshold v fb as a % of v ref , test mode 85 89 93 % falling hysteresis v fb as a % of v ref , test mode 2 3.5 5 % power-good drive v in = 3v, pgood = 0.4v, en = gnd 7.2 ma power-good leakage v in = pgood = 5.5v 1 a protection features undervoltage monitor undervoltage trip threshold v fb as a % of v ref , test mode 71 75 79 % undervoltage recovery threshold v fb as a % of v ref , test mode 84 88 92 % overcurrent monitor overcurrent trip level i ocx = 60a, test mode (note 14) 5.35 7.35 a i ocx = 240a, test mode (note 14) 23 26 a curent share slave load current master load current = 12a, v in = 3.3v, v out = 0.8v, sc1 = ishsl = m/s = 0, sc0 = ishen = fsel = 1, sync = 1mhz external, 500nh inductor (notes 12, 13) 712 17 a master load current = 12a, v in = 3.3v, v out = 1.8v, sc0 = ishsl= m/s = 0, sc1 = ishen = fsel = 1, sync = 1mhz external, 500nh inductor (notes 12, 13) 712 17 a master load current = 12a, v in = 5.0v, v out = 1.8v, sc0 = ishsl = m/s = 0, sc1 = ishen = fsel = 1, sync = 1mhz external, 500nh inductor (notes 12, 13) 712 17 a master load current = 12a, v in = 5.0v, v out = 2.5v, ishsl = m/s = 0, sc0 = sc1 = ishen = fsel = 1, sync=1mhz external, 500nh inductor (notes 12, 13) 712 17 a ishx, ishrefx, tri-state leakage current v in = 5.5v, en = gnd -1 0 1 a master ishcom pull-up resistance ishcom = -50a 6.5 10 13 k slave ishcom input leakage current v in = ishsl = 5.5v -1 1 a slave ishcom pull-down resistance ishsl = v in , en = gnd, ishcom = 7.2ma 35 75 125 slave ishcom input high voltage ishsl = v in 42 52 62 % of v in slave ishcom input low voltage ishsl = v in 26 36 46 % of v in slave ishcom input voltage hysteresis ishsl = v in 716 24% of v in electrical specifications unless otherwise noted, v in = avdd = dvdd = pvinx = en = fsel = m/s = sc0 = sc1= 3v to 5.5v; gnd = agnd = dgnd = pgndx = ishx = ishcom = ishen = ishrefx = ishsl = tdi = tdo = tpgm = 0v; fb = 0.65v; porsel = v in for 4.5v v in 5.5v and gnd for v in < 4.5v; lxx = sync = open circuit; ocx is connected to ocssx with a 10k resistor; ocx is connected to gnd with a 4.99k resistor shunted by a 6.8nf capa citor; pgood is pulled up to v in with a 1k resistor; ref is bypassed to gnd with a 220nf capacitor; ss is bypassed to gnd with a 100nf capacitor; t a = t j = -55c to +125c; post 100krad(si). (note 6). (continued) parameter test conditions min (note 10) typ max (note 10) units
isl70002seh 11 fn8264.1 april 5, 2012 ishsl input leakage current -1 1 a ishsl input high voltage v in - 0.5 1.3 v ishsl input low voltage 1.2 0.5 v slope compensation sc1 = sc0 = v in 5.9 13.4 17.7 a/s sc1 = v in , sc0 = gnd 3.0 6.7 8.8 a/s sc1 = gnd, sc0 = v in 1.5 3.4 4.5 a/s sc1 = sc0 = gnd 0.7 1.7 2.2 a/s fsel = gnd, sc1 = sc0 = v in 2.9 6.6 8.8 a/s fsel = gnd, sc1 = v in , sc0 = gnd 1.4 3.3 4.5 a/s fsel = gnd, sc1 = gnd, sc0 = v in 0.7 1.6 2.2 a/s fsel = gnd, sc1 = sc0 = gnd 0.3 0.8 1.2 a/s notes: 9. typical values shown reflect t a = t j = +25c operation and are not guaranteed. 10. parameters with min and/or max limits are 100% test ed at -55c, +25c and +125c, unless otherwise specified. 11. limits do not include tolerance of external feedback resistors. the 0a to 12a output current range may be reduced by minimum lxx on time and minimum lxx off time specifications. 12. limits established by characterization or analysis and are not production tested. 13. tested sequencially on lx2, lx6 and lx9. 14. tested sequencially on lx2 and lx6 at 535ma to 735ma and 2.3a to 2.6a. 15. tested in accordance with mil- std-883, method 1019, condition a. electrical specifications unless otherwise noted, v in = avdd = dvdd = pvinx = en = fsel = m/s = sc0 = sc1= 3v to 5.5v; gnd = agnd = dgnd = pgndx = ishx = ishcom = ishen = ishrefx = ishsl = tdi = tdo = tpgm = 0v; fb = 0.65v; porsel = v in for 4.5v v in 5.5v and gnd for v in < 4.5v; lxx = sync = open circuit; ocx is connected to ocssx with a 10k resistor; ocx is connected to gnd with a 4.99k resistor shunted by a 6.8nf capa citor; pgood is pulled up to v in with a 1k resistor; ref is bypassed to gnd with a 220nf capacitor; ss is bypassed to gnd with a 100nf capacitor; t a = t j = -55c to +125c; post 100krad(si). (note 6). (continued) parameter test conditions min (note 10) typ max (note 10) units
isl70002seh 12 fn8264.1 april 5, 2012 typical performance curves figure 5. overcurrent reference voltage figure 6. ref voltage vs v in figure 7. osc frequency vs v in figure 8. lxx minimum on time vs v in figure 9. sustained output current with overcurrent disabled figure 10. operatin g current vs v in 596.0 596.5 597.0 597.5 598.0 598.5 599.0 599.5 600.0 -55 -35 -15 5 25 45 65 85 105 125 ocb oca temperature (c) voltage (mv) 598.0 598.5 599.0 599.5 600.0 600.5 601.0 601.5 602.0 -55 -35 -15 5 25 45 65 85 105 125 v in = 5.5v v in = 3v temperature (c) v ref (mv) 900 925 950 975 1,000 1,025 1,050 -55 -35 -15 5 25 45 65 85 105 125 v in = 5.5v v in = 3v temperature (c) osc frequency (khz) 125 150 175 200 225 250 275 -55 -35 -15 5 25 45 65 85 105 125 temperature (c) v in = 3v v in = 5.5v minimum on time (ns) 0 5 10 15 20 25 30 -55 -35 -15 5 25 45 65 85 105 125 temperature (c) ocx disabled sustained output current (a) 35 40 45 50 55 60 65 70 -55 -35 -15 5 25 45 65 85 105 125 temperature (c) v in = 5.5v v in = 3.6v operating current (ma)
isl70002seh 13 fn8264.1 april 5, 2012 figure 11. lx on-resistance, all power blocks in parallel, v in = 3v typical performance curves (continued) 0 5 10 15 20 25 30 -55 -35 -15 5 25 45 65 85 105 125 temperature (c) nfet pfet on-resistance (m )
isl70002seh 14 fn8264.1 april 5, 2012 functional description the isl70002seh is a monolithic , fixed frequency, current-mode synchronous buck regulator. tw o isl70002seh devices can be used to provide a total dc/dc solution for fpgas, cplds, dsps and cpus. power blocks the power output stage of the regulator consists of ten power blocks that are paralleled to provide full 12a output current capability. the block diagram in figure 12 shows a top level view of the individual power blocks. each power block has a power supply input pin, pvinx, a phase output pin, lxx, and a power supply ground pin, pgndx. all pvinx pins must be connected to a common power supply rail and all pgndx pins must be connected to a common ground. lxx pins should be connected to the output inductor based on the required load current, but must include the lx2, lx6 and lx9 pins. for example, if 6a of output current is needed, any five lxx pins can be connected to the inductor as long as three of them are the lx2, lx6 and lx9 pins. the unused lxx pins should be left unconnected. connecting all ten lxx pins to the output inductor provides a maximum 12 a of output current at +150c die temperature. see the ?typical application schematic? on page 6 for pin connection guidance. power blocks 2, 6 and 9 contain the master pilot devices, which provides current feedback and this is why they must be connected to the output inductor. main control loop during normal operation, the internal top power switch is turned on at the beginning of each clock cycle. current in the output inductor ramps up until the current comparator trips and turns off the top power mosfet. then the bottom power mosfet turns on and the inductor current ramps down for the rest of the cycle. the current comparator compares the output current at the current ripple peak to the scaled pilot current. the error amplifier monitors v out and compares it with an internal reference voltage. the output voltage of the error amplifier creates a proportional current to the pilot. if v out is low, the current level of the pilot is increased and the trip off current level of the output is increased. the increased output current raises v out until it is in agreement with the reference voltage. output voltage selection the output voltage of the isl700 02seh can be adjusted using an external resistor divider as shown in figure 13. r t should be selected as 1k to mitigate see. r t should be shunted by a 4.7nf ceramic capacitor, c c , to mitigate see and to improve loop stability margins. the ref pin sh ould be bypassed to agnd with a 220nf ceramic capacitor to mitigate see. it should be noted that no current (sourcing or sinking) is available from the ref pin. r b can be determined from equation 3. the designer can configure the output voltage fr om 0.8v to 85% of the input voltage. the minimum on time determines the lowest output voltage, so when vin = 5.5v and the switching frequency is 500khz this parameter limits the regulated output voltage to about 0.8v or greater. it increases at the 1m hz switching frequency to about 1.6v or greater. the minimum on time increases by about 9% at v in = 3v, but the 500khz output voltage is not limited by the minimum on time and the 1mhz minimum v out is approximately 0.9v. switching frequency/synchronization the isl70002seh features an in ternal oscillator running at a fixed frequency of either 500khz or 1mhz 15% over recommended operating conditio ns. when the fsel pin is grounded the oscillator operated at 500khz, and if fsel is connected to dvdd it operates at 1mhz. the regulator can be configured to run from the internal oscillator or can be synchronized to another isl70002seh or an see hardened external clock with a frequency range of 500khz to 1mhz (20%). to run the regulator from the internal oscillator, connect the m/s pin to dvdd. in this case the output of the internal oscillator power block 10 pgnd10 power block 9 power block 8 power block 1 power block 2 power block 3 pvin10 pgnd9 pvin9 pgnd8 pvin8 pgnd1 pvin1 pgnd2 pvin2 pgnd3 pvin3 figure 12. power block diagram lx2 lx1 lx3 lx10 lx9 lx8 power block 7 power block 6 power block 4 power block 5 pgnd4 pvin4 pgnd5 pvin5 lx4 lx5 pgnd7 pvin7 pgnd6 pvin6 lx7 lx6 note: shaded blocks indicate pilot current pwma and ocpa pwmb and ocpb pwmc and overcurrent sensors. figure 13. output voltage selection fb c out l out v out lxx r t r b v ref error amplifier ref c ref - + c c v ref = 0.6v c ref = 220nf r t = 1k c c = 4.7nf r b r t v ref v out v ref ? ------------------------------------- ? = (eq. 3)
isl70002seh 15 fn8264.1 april 5, 2012 appears on the sync pin. to synchronize the regulator to the sync output of another isl70002seh regulator or to an see hardened external clock, connect the m/s pin to dgnd. in this case the sync pin is an input that accepts an external synchronizing signal. when m/s is connected to dgnd, the isl70002seh is synchronized 180 out-of-phase with respect to the sync input of a master configured regulator sync output or to an external clock. two phase operation the isl70002seh is capable of operating 2 ics as a single two phase regulator with nearly twice the load current capacity. in this mode, a redundant current sharing bus balances the load current between the two devices and communicates any fault conditions. one isl70002seh is designated the master and the other the slave. the master ishsl pin is connected to dgnd and the slave ishsl pin is connected to dvdd. the ishen pins on both master and slave are connected to dvdd. the sync, isha, ishb, ishc, ishrefa, ishrefb, ishrefc, ishcom and fb pins are connected from the master to the slave and the ref pins are tied with a 10 resistor. configured this way, the two phase regulator nearly doubles the load current capacity, limited only by the current share match tolerance. the isl70002seh ics operate 180 out-of-phase to minimize the input ripple current, effectively operating as a single ic at twice the switching frequency. the master phase uses the falling edge of the sync clock to initiate the master switching cycle with the non-overlap period before the rising edge of lx, while the slave phase internally inverts the sync input and uses the falling edge of the inverted copy to start it?s switching cycle. this is independent of whether the master phase is configured for an external clock (master m/s = dgnd) or its internal clock (master m/s = dvdd). the master error amplifier and compensation controls the two phase regulator while the slave error amplifier is disabled. the schematic in fi gure 3 shows the complete connections for the master and slave. operation initialization the isl70002seh initializes based on the state of the power-on reset (por) monitor of the pvinx inputs and the state of the en input. successful initialization prompts a soft-start interval and the regulator begins slowly ramping the output voltage. once the commanded output voltage is within the proper window of operation, the power-good signal changes state from low to high indicating proper regulator operation. power-on reset the por circuitry prevents the controller from attempting to soft- start before sufficient bias is present at the pvinx pins. the por threshold of the pvinx pi ns is controlled by the porsel pin. for a nominal 5v supply voltage, porsel should be connected to dvdd. for a nominal 3.3v supply voltage, porsel should be connected to dgnd. for nominal supply voltages between 5v and 3.3v, porsel should be connected to dgnd. the por rising and falling threshol ds are shown in the ?electrical specifications? table on page 9. hysteresis between the rising and falling thresholds insures that small perturbations on pvinx seen during turn-on/turn-off of the regulator do not cause inadvert ent turn-off/turn-on of the regulator. when the pvinx pins are below the por rising threshold, the internal synchron ous power mosfet switches are turned off and the lxx pins are held in a high-impedance state. enable and disable after the por input requirement is met, the isl70002seh remains in shutdown until the vo ltage at the enable input rises above the enable threshold. as shown in figure 14, the enable circuit features a comparator type input. in addition to simple logic on/off control, the enable circuit allows the level of an external voltage to precisely gate the turn-on/turn-off of the regulator. an internal i en current sink with a typical value of 11a is only active when the voltage on the en pin is below the enable threshold. the current sink pulls the en pin low. as v control rises, the enable level is not set exclusively by the resistor divider from v control . with the current sink active, the enable level is defined by equation 4. r1 is the resistor from the en pin to v control and r2 is the resistor from the en pin to the agnd pin. once the voltage at the en pin re aches the enable threshold, the i en current sink turns off. with the part enabled and the i en current sink off, the disable level is set by the resistor divider. the disable level is defined by equation 5. the difference between the enable and disable levels provides adjustable hysteresis so that noise on v control does not interfere with the enabling or disabling of the regulator. the en pin should be bypassed to the agnd pin with a 10nf ceramic capacitor to mitigate see . v enable v ref 1 r1 r2 ------- - + ? i en r1 ? + = (eq. 4) v disable v ref 1 r1 r2 ------- - + ? = (eq. 5) figure 14. enable circuit - + v ref en pvinx v in por logic v control r1 r2 i en enable comparator c en v ref = 0.6v i en = 11a c en = 10nf
isl70002seh 16 fn8264.1 april 5, 2012 soft-start once the por and enable circuits are satisfied, the regulator initiates a soft-start. figure 15 shows that the soft-start circuit clamps the error amplifier referenc e voltage to the voltage on an external soft-start capacitor connected to the ss pin. the soft-start capacitor is charged by an internal i ss current source (23a typical). as the soft-start capacitor is charged, the output voltage slowly ramps to the set point determined by the reference voltage and the feedback network. once the voltage on the ss pin is equal to the intern al reference voltage (600mv), the soft-start interval is comple te though the ss pin voltage continues to rise to approximat ely 1.4v. pgood is enabled after ss reached to 1.4v. the controlled ramp of the output voltage reduces the inrush current during start-up. the soft-start output ramp interval is defined in equa tion 6 and is adjustable from approximately 2ms to 200ms. the value of the soft-start capacitor, c ss , should range from 82nf to 8.2f, inclusive. the peak inrush current can be computed from equation 7. the soft-start interval should be selected long enough to insure that the peak in-rush current plus the peak output load current does not exceed the ss overcurrent trip level of the regulator. the soft-start capacitor is immediately discharged by a 2.2 resistor whenever por conditions are not met or en is pulled low. the soft-start discharge time is equal to 256 clock cycles. power-good the power-good (pgood) pin is an open-drain logic output which indicates when the output voltag e of the regulator is within regulation limits. the power-good pin pulls low during shutdown and remains low when the controller is enabled. after a successful soft-start, the pgood pin releases and the voltage rises with an external pull-up resistor. the power-good signal transitions low immediately when the en pin is pulled low. the power-good circuitry monitors the fb pin and compares it to the rising and falling threshol ds shown in the ?electrical specifications? table on page 10. if the feedback voltage exceeds the typical rising limit of 111% of the reference voltage, the pgood pin pulls low. the pgood pin continues to pull low until the feedback voltage falls to a typical of 107.5% of the reference voltage. if the feedback voltage drops below a typical of 89% of the reference voltage, the pgood pin pulls low. the pgood pin continues to pull low until the feedback voltage rises to a typical 92.5% of the reference voltage. the pgood pin then releases and signals the return of the output voltage within the power- good window. the pgood pin can be pulled up to any voltage from 0v to 5.5v, independent of the supply voltag e. the pull-up resistor should have a nominal value from 1k to 10k . the pgood pin should be bypassed to dgnd with a 10nf ceramic capacitor to mitigate see. slope compensation the sc0 and sc1 pins select four levels of current mode slope compensation. in current mode buck regulators, when the duty cycle approaches and exceeds 50% the regulator will operate in sub-harmonic oscillation without slope compensation. slope compensation is widely considered unnecessary if the duty cycle is held below 40% and provides better phase margin. transient duty cycles must be taken into consideration when selecting the level of slope compensation. the following table describes the amount of effective current that is added the output powerstage signal that is used in the pwm modulator. fault monitoring and protection the isl70002seh actively monito rs output voltage and current to detect fault conditions. faul t conditions trigger protective measures to prevent damage to the regulator and external load device. undervoltage protection a hysteretic comparator monitors the fb pin of the regulator. the feedback voltage is compared to an undervoltage threshold that is a fixed percentage of the reference voltage. once the t ss c ss v ref i ss --------------- ? = (eq. 6) i inrush c out v out t ss --------------- - ? = (eq. 7) figure 15. soft-start circuit - + v ref fb pwm logic i ss error amplifier ref c ref v out r t r b + ss c ss v ref = 0.6v i ss = 23a r d r d = 2.2 table 1. fsel sc1 sc0 slope comp (a/s) dgnd dgnd dgnd 0.8 dgnd dgnd dvdd 1.6 dgnd dvdd dgnd 3.3 dgnd dvdd dvdd 6.6 dvdd dgnd dgnd 1.7 dvdd dgnd dvdd 3.4 dvdd dvdd dgnd 6.7 dvdd dvdd dvdd 13.4
isl70002seh 17 fn8264.1 april 5, 2012 comparator trips on two consecutive switching cycles, indicating a valid undervoltage condition, the undervoltage protection logic shuts down the regulator. if the feedback voltage rises back above the undervoltage threshol d plus a specified amount of hysteresis outlined in the ?electrical specifications? table on page 10 after the first detection and before the second, normal operation continues. after the regulator shuts down, it enters a delay interval, equivalent to the selected soft-start interval. the undervoltage counter is reset entering the delay interval. the protection logic initiates a normal soft-start once the delay interval ends. if the output successfully soft-starts, th e power-good signal goes high and normal operation continues. if undervoltage conditions continue to exist during the soft-start interval, the undervoltage counter must overflow before the regulator shuts down again. this hiccup mode continues indefinitely until the output soft- starts successfully. overcurrent protection a pilot devices integrated into the pmos transistor of power blocks 2 and 6 samples the inductor curr ent each cycle. this current feedback is scaled and compared to an overcurrent threshold based on the overcurrent resistor connected from ocx to agnd. if the sampled current exceeds the overcurrent threshold, an overcurrent counter increments. if the sampled current falls below the threshold before the counter ov erflows, the counter is reset. once the overcurrent counter reaches 2, the regulator shuts down. after the regulator shuts down, it enters a delay interval, equivalent to the soft-start interval, allowing the device to cool. the overcurrent counter is reset entering the delay interval. the protection logic initiates a normal soft-start once the delay interval ends. if the output successfully soft-starts, the power- good signal goes high and no rmal operation continues. if overcurrent conditions continue to exist during the soft-start interval, the overcurrent counter must overflow before the regulator shut downs the output again. this hiccup mode continues indefinitely until the output soft-starts successfully. component selection guide this design guide is intended to provide a high-level explanation of the steps necessary to create a power converter. it is assumed the reader is familiar with many of the basic skills and techniques referenced below. in addition to this guide, intersil provides a complete evaluation board that includes schematic, bom, and an example pcb layout. output filter design the output inductor and the output capacitor bank together form a low-pass filter responsible for smoothing the pulsating voltage at the phase node. the filter must also provide the transient energy until the regulator can respond. since the filter has low bandwidth relative to the switching frequency, it limits the system transient response. the ou tput capacitors must supply or sink current while the current in the output inductor increases or decreases to meet the load demand. output capacitor selection the critical load parameters in choosing the output capacitors are the maximum size of the load step ( i step ), the load-current slew rate (di/dt), and the maximum a llowable output voltage deviation under transien t loading ( v max ). capacitors are characterized according to their capacitance, esr (equivalent series resistance) and esl (equivalent series inductance). at the beginning of a load transient, the output capacitors supply all of the transient current. the output voltage will initially deviate by an amount approximated by the volt age drop across the esl. as the load current increases, the volt age drop across the esr increases linearly until the load current reaches its final value. neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount shown in equation 8. the filter capacitors selected must have sufficiently low esl and esr such that the total output voltage deviation is less than the maximum allowable ripple. most capacitor solutions rely on a mixture of high frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but larger esr. minimizing the esl of the high-frequency capacitors allows them to support the output voltage as the current increases. minimizing the esr of the bulk capacitors allows them to supply the increased current with less output voltage deviation. ceramic capacitors with x7r dielectric are recommended. alternately, a combination of lo w esr solid tantalum capacitors and ceramic capacitors with x7r dielectric may be used. the esr of the bulk capacitors is responsible for most of the output voltage ripple. as the bulk capacitors sink and source the inductor ac ripple current, a voltage, v p-p(max) , develops across the bulk capacitor according to equation 9. output inductor selection once the output capacitors are selected, the maximum allowable ripple voltage, v p-p(max) , determines the lower limit on the inductance as shown in equation 10. since the output capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. the output inductor must be capable of assuming the entire load current before the output voltage decreases more than v max . this places an upper li mit on inductance. equation 11 gives the upper limit on output inductance for the case when the trailing edge of the current transient causes the greater output voltage deviation than the leading edge. equation 12 addresses the leading edge. normally, the trailing edge dictates the inductance selection because duty cycles are usually <50%. nevertheless, both inequalities should be evaluated, and inductance should be governed based on the lower of the two results. in each equation, l out is the output inductance, c out is v max esl di dt ---- - esr i step [] + (eq. 8) v p-p(max) esr v in v out ? () v out l out f s v in ---------------------------------------------------- - = (eq. 9) l out esr v in v out ? () v out f s v in v p-p(max) ------------------------------------------------------ (eq. 10)
isl70002seh 18 fn8264.1 april 5, 2012 the total output capacitance and i l(p-p) is the peak to peak ripple current in the output inductor. the other concern when selecting an output inductor is to insure there is adequate slope compen sation when the regulator is operated above 40% duty cycle. in most cases, the maximum slope compensation setting (sc1 = dvdd, sc0 = dvdd provides sufficient phase margin, theref ore this is the recommended configuration. input capacitor selection input capacitors are responsible for sourcing the ac component of the input current flowing into the switching power devices. their rms current capacity must be sufficient to handle the ac component of the current drawn by the switching power devices which is related to duty cycle. the maximum rms current required by the regulator is closely approximated by equation 13. the important parameters to cons ider when selecting an input capacitor are the voltage rating and the rms ripple current rating. for reliable operation, select capacitors with voltage ratings at least 1.5x greater than the maximum input voltage. the capacitor rms ripple current rating should be higher than the largest rms ripple current required by the circuit. a combination of low esr tantalum capacitors and ceramic capacitors with x7r dielectric are recommended. the isl70002seh requires a minimu m effective input capacitance of 100f for stable operation. pcb design pcb design is critical to high-frequency switching regulator performance. careful component placement and trace routing are necessary to reduce voltage spikes and minimize undesirable voltage drops. selection of a suitable thermal interface material is also requir ed for optimum heat dissipation and to provide lead strain relief. pcb plane allocation four layers of two ounce copper are recommended. layer 2 should be a dedicated ground pl ane with all critical component ground connections made with vias to this layer. layer 3 should be a dedicated power plane split between the input and output power rails. layers 1 and 4 should be used primarily for signals, but can also provide additional power and ground islands as required. pcb component placement components should be placed as close as possible to the ic to minimize stray inductance an d resistance. prioritize the placement of bypass capacitors on the pins of the ic in the order shown: ref, ss, avdd, dvdd, pvinx (high frequency capacitors), en, pgood, pvinx (bulk capacitors). locate the output voltage resistive divider as close as possible to the fb pin of the ic. the top leg of the divider should connect directly to the pol (point of load) and the bottom leg of the divider should connect directly to agnd. the junction of the resistive divider should conn ect directly to the fb pin. a small series r-c snubber connec ted from the lxx pins to the pgndx pins may be used to damp high frequency ringing on the lxx pins if desired. pcb layout use a small island of copper to co nnect the lxx pins of the ic to the output inductor on layers 1 and 4. void the copper on layers 2 and 3 adjacent to the island to minimize capacitive coupling to the power and ground planes. place most of the island of layer 4 to minimize the amount of copper that must be voided from the ground plane (layer 2). keep all other signal trac es as short as possible. for an example layout refer to an1732 . thermal management for optimum thermal performance, place a pattern of vias on the top layer of the pcb directly underneath the ic. connect the vias to the ground plane on layer 2, which serves as a heatsink. to insure good thermal contact, ther mal interface material such as a sil-pad or thermally conductive epoxy should be used to fill the gap between the vias and the bottom of the ic. lead strain relief the package leads protrude from the bottom of the package and the leads are slightly bent to provide strain relief. l out 2c out v out ?? i step () 2 -------------------------------------------- v max i l(p-p) esr ? () ? (eq. 11) l out 2c out ? i step () 2 ---------------------------- - v max i l(p-p) esr ? () ? v in v out ? ?? ?? (eq. 12) i rms i out v out v in ----------------- 1 1 3 --- + v in v out ? i out l out f s --------------------------------------------------- - v out v in ----------------- ?? ?? ?? 2 = (eq. 13)
isl70002seh 19 fn8264.1 april 5, 2012 weight characteristics weight of packaged device 1.43 grams typical die characteristics die dimensions 8300m x 8300m (327 mils x 327 mils) thickness: 300m 25. 4m (12 mils 1 mil) interface materials glassivation type: silicon oxide and silicon nitride thickness: 0.3m 0.03m and 1.2m 0.12m top metallization type: alcu (0.5%) thickness: 2.7m 0.4m substrate type: silicon isolation: junction backside finish silicon assembly related information substrate and metal lid potential pgnd additional information worst case current density < 2 x 10 5 a/cm 2 transistor count 28,160 layout characteristics step and repeat 8300m x 8300m metallization mask layout isl70002seh fb isha ishrefa ishb ishrefb ishc ishrefc avdd agnd dgnd dvdd ss pgood ishcom ishsl ishen porsel tdo tdi tpgm gnd sync m/s fsel pvin10 pvin9 sc0 sc1 en ocssb ocb ocssa oca ref lx10 pgnd10 lx9 pgnd9 pvin8 lx8 pgnd8 pvin6 lx6 pgnd6 pvin7 lx7 pgnd7 pvin4 lx4 pgnd4 pvin5 lx5 pgnd5 pvin3 lx3 pgnd3 pvin2 lx2 pgnd2 pvin1 lx1 pgnd1
isl70002seh 20 fn8264.1 april 5, 2012 table 2. layout x-y coordinates pad name pad number x ( m) y ( m) dx ( m) dy ( m) bond wires size (0.001?) fb 1 275 7497 135 135 1.5 isha 2 275 7117 135 135 1.5 ishrefa 3 275 6737 135 135 1.5 ishb 4 275 6357 135 135 1.5 ishrefb 5 275 5977 135 135 1.5 ishc 6 275 5597 135 135 1.5 ishrefc 7 275 5217 135 135 1.5 avdd 8 335 4672 254 254 3 agnd 9 335 3972 254 254 3 dgnd 10 335 3272 254 254 3 dvdd 11 335 2572 254 254 3 ss 12 275 2021 135 134 1.5 pgood 13 275 1671 135 135 1.5 1shcom 14 275 1321 135 135 1.5 ishsl 15 275 971 135 135 1.5 ishen 16 275 621 135 135 1.5 porsel 17 275 275 135 135 1.5 tdo 18 635 275 135 135 1.5 tdi 19 995 275 135 135 1.5 tpgm 20 1355 275 135 135 1.5 gnd 21 1715 275 135 135 1.5 sync 22 2075 275 135 135 1.5 m/s 23 2435 275 135 135 1.5 fsel 24 2795 275 135 135 1.5 pvin10 25 3463 336 254 254 3 lx10 26 3693 1222 254 254 3 pgnd10 27 3905 2074 254 254 3 pgnd9 28 5281 2074 254 254 3 lx9 29 5494 1222 254 254 3 pvin9 30 5723 336 254 254 3 pvin8 31 6115 778 254 254 3 lx8 32 6967 566 254 254 3 pgnd8 33 7853 336 254 254 3 pgnd7 34 6115 2154 254 254 3 lx7 35 6967 2366 254 254 3 pvin7 36 7853 2596 254 254 3 pvin6 37 7853 2965 254 254 3 lx6 38 6967 3195 254 254 3 pgnd6 39 6115 3408 254 254 3
isl70002seh 21 fn8264.1 april 5, 2012 pgnd5 40 6115 4784 254 254 3 lx5 41 6967 4996 254 254 3 pvin5 42 7853 5226 254 254 3 pvin4 43 7853 5595 254 254 3 lx4 44 6967 5825 254 254 3 pgnd4 45 6115 6037 254 254 3 pgnd3 46 7853 7855 254 254 3 lx3 47 6967 7625 254 254 3 pvin3 48 6115 7413 254 254 3 pvin2 49 5723 7855 254 254 3 lx2 50 5494 6969 254 254 3 pgnd2 51 5281 6117 254 254 3 pgnd1 52 3905 6117 254 254 3 lx1 53 3693 6969 254 254 3 pvin1 54 3463 7855 254 254 3 sc0 55 2836 7914 135 135 1.5 sc1 56 2476 7914 135 135 1.5 en 57 2116 7914 135 135 1.5 ocssb 58 1756 7914 135 135 1.5 ocb 59 1396 7914 135 135 1.5 ocssa 60 1036 7914 135 135 1.5 oca 61 676 7914 135 135 1.5 ref 62 316 7914 135 135 1.5 table 2. layout x-y coordinates (continued) pad name pad number x ( m) y ( m) dx ( m) dy ( m) bond wires size (0.001?)
isl70002seh 22 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8264.1 april 5, 2012 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: isl70002seh to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change march 30, 2012 fn8264.1 figure 2 on page 1changed ?slave? to ?mas ter? to ch1 and added ?at 86.4mev/mg/cm2" to figure title. ?soft-start? on page 16 changed in 2nd to last sentence ?...range from 8.2nf...? to ?...range from 82nf...? ?layout x-y coordinates? on page 20 changed in bond wires column for ?ishb? from ?1.51? to ?1.5? march 27, 2012 fn8264.0 initial release
isl70002seh 23 fn8264.1 april 5, 2012 package outline drawing r64.a 64 ceramic quad flatpack package (cqfp) rev 3, 1/12 top view side view notes: 1. all dimensions are in inches (millimeters). 0.010 (0.25) 1.275 (32.39) 0.011 (0.279) min 1.055 (26.80) 0.567 (14.40) 0.547 (13.90) pin 1 index 0.006 (0.15) 1.275 (32.39) 1.055 (26.80) 0.027 (0.685) 0.023 (0.585) 0.567 (14.40) 0.547 (13.90) 0.350 (8.89) 0.250 (6.35) pin 1 0.0075 (0.188) 0.005 (0.125) 0.135 (3.43) 0.065 (1.65) 0.0034 (0.087) min 0.008 (0.20) ref detail ?a? see detail ?a? (0.030) (0.76) ref (0.156) chamfer 0.012 (0.30) ref (0.019) ref index paste (2.69) ref 2x 0.106 64 2x0.48 1 (3.97) ref 0.081 (2.05) ref bottom view 0.380 (9.655) 0.370 (9.395) 0.100 (2.537) 0.085 (2.157) 0.020 (0.51) 0.016 (0.41) 0.055 (1.40) 0.045 (1.14) detail ?b? see detail "b" area

▲Up To Search▲

Price & Availability of ISL70002SEHEVAL1Z

	To Download ISL70002SEHEVAL1Z Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .